The technology disclosed in this specification relates to a comparator which receives a differential input signal pair, and performs a comparison operation with respect to a differential voltage across the differential input signal pair in synchronism with a clock signal.
In recent years, as the speed of information communication increases, and the speed and the capacity of optical disk pickups increase, there has been a need for high speed and wide input bandwidth analog-to-digital converters (ADCs), further having reduced areas and reduced power consumption for cost reduction.
FIG. 6 shows an example configuration of a dynamic comparator used for a comparator included in a high speed and low power consumption ADC. The comparator shown in FIG. 6 includes an input transistor section 10 having NMOS transistors m0a and m0b, and a positive feedback section (cross-coupled inverter latch section) 20 having NMOS transistors m1a and m1b and PMOS transistors m3a and m3b. 
The gate terminals of the transistors m1a and m3a and the drain terminal of the transistor m3b are coupled to an output terminal q, and the gate terminals of the transistors m1b and m3b and the drain terminal of the transistor m3a are coupled to an output terminal qb.
An NMOS transistor m2a is coupled between the drain terminals of the NMOS transistor m1a and the PMOS transistor m3a; and the NMOS transistor m2a operates as a switch in synchronism with a clock signal CLK. An NMOS transistor m2b is coupled between the drain terminals of the NMOS transistor m1b and the PMOS transistor m3b; and the NMOS transistor m2b operates as a switch in synchronism with the clock signal CLK.
The source terminals of the PMOS transistors m3a and m3b are coupled to a power supply VDD. A PMOS transistor m4a is coupled between the drain terminal of the PMOS transistor m3a and the power supply VDD; and the PMOS transistor m4a operates as a switch in synchronism with the clock signal CLK. A PMOS transistor m4b is coupled between the drain terminal of the PMOS transistor m3b and the power supply VDD; and the PMOS transistor m4b operates as a switch in synchronism with the clock signal CLK.
The gate terminal of the NMOS transistor m0a is coupled to the positive terminal “ia” of a differential input signal pair; the source terminal is coupled to a reference potential VSS; and the drain terminal is coupled to the source terminal of the NMOS transistor m1a. The gate terminal of the NMOS transistor m0b is coupled to the negative terminal “ib” of the differential input signal pair; the source terminal is coupled to the reference potential VSS; and the drain terminal is coupled to the source terminal of the NMOS transistor m1b. 
The gate terminals of the NMOS transistor m2a and m2b, and the gate terminals of the PMOS transistor m4a and m4b are coupled to the clock signal CLK.
The input transistor section 10 outputs a result of comparison between the positive terminal ia and the negative terminal ib of the differential input signal pair, to the positive feedback section 20.
When the clock signal CLK is at or above a predetermined level (hereinafter referred to as “High”), the PMOS transistors m4a and m4b open (turn off), and the NMOS transistors m2a and m2b conduct (turn on); thus, the positive feedback section 20 amplifies the result of comparison output from the input transistor section 10, holds the amplified result, and outputs the amplified result as digital signals to the output terminals q and qb.
When the clock signal CLK is at or below a predetermined level (hereinafter referred to as “Low”), the PMOS transistors m4a and m4b conduct (turn on), and the voltages of the output terminals q and qb are set to the power supply voltage VDD, that is, reset to High. In addition, the NMOS transistors m2a and m2b open (turn off), thereby causing the current paths to be disconnected, and thus no power to be consumed.
Thus, such a dynamic comparator is advantageous in that the power consumption is reduced. This field of technology is described in, for example, Japanese Patent Publications Nos. H04-043718 and 2003-158456.